6.2.27 CSI Packet Interrupt Force Register
Used for test purposes. Triggers CSI_INT_ST_PKT interrupt events individually without the need to activate the conditions that trigger the interrupt sources.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: The corresponding interrupt source is forced.
| Name: | CSI_INT_FORCE_PKT |
| Offset: | 0x128 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FORCE_VC3_ERR_ECC_CORRECTED | FORCE_VC2_ERR_ECC_CORRECTED | FORCE_VC1_ERR_ECC_CORRECTED | FORCE_VC0_ERR_ECC_CORRECTED | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FORCE_ERR_ID_VC3 | FORCE_ERR_ID_VC2 | FORCE_ERR_ID_VC1 | FORCE_ERR_ID_VC0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |