Reading the CSI_INT_ST_LINE register does not clear the interrupt pin.
The following configuration values are valid for all listed bit names of this
register:
0: No event occurred since the last read of the register.
1: An event occurred since the last read of the register.
Name:
CSI_INT_ST_LINE
Offset:
0x130
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
ERR_L_SEQ_DI7
ERR_L_SEQ_DI6
ERR_L_SEQ_DI5
ERR_L_SEQ_DI4
ERR_L_SEQ_DI3
ERR_L_SEQ_DI2
ERR_L_SEQ_DI1
ERR_L_SEQ_DI0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
ERR_L_BNDRY_MATCH_DI7
ERR_L_BNDRY_MATCH_DI6
ERR_L_BNDRY_MATCH_DI5
ERR_L_BNDRY_MATCH_DI4
ERR_L_BNDRY_MATCH_DI3
ERR_L_BNDRY_MATCH_DI2
ERR_L_BNDRY_MATCH_DI1
ERR_L_BNDRY_MATCH_DI0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit 23 – ERR_L_SEQ_DI7 Error in the
Sequence of Lines for VC7 and DT7 (cleared on read)
Bit 22 – ERR_L_SEQ_DI6 Error in the
Sequence of Lines for VC6 and DT6 (cleared on read)
Bit 21 – ERR_L_SEQ_DI5 Error in the
Sequence of Lines for VC5 and DT5 (cleared on read)
Bit 20 – ERR_L_SEQ_DI4 Error in the
Sequence of Lines for VC4 and DT4 (cleared on read)
Bit 19 – ERR_L_SEQ_DI3 Error in the
Sequence of Lines for VC3 and DT3 (cleared on read)
Bit 18 – ERR_L_SEQ_DI2 Error in the Sequence of Lines for VC2 and DT2 (cleared on
read)
Bit 17 – ERR_L_SEQ_DI1 Error in the Sequence of Lines for VC1 and DT1 (cleared on
read)
Bit 16 – ERR_L_SEQ_DI0 Error in the Sequence of
Lines for VC0 and DT0 (cleared on read)
Bit 7 – ERR_L_BNDRY_MATCH_DI7 Error Matching Line
Start with Line End for VC7 and DT7 (cleared on read)
Bit 6 – ERR_L_BNDRY_MATCH_DI6 Error Matching Line
Start with Line End for VC6 and DT6 (cleared on read)
Bit 5 – ERR_L_BNDRY_MATCH_DI5 Error Matching Line
Start with Line End for VC5 and DT5 (cleared on read)
Bit 4 – ERR_L_BNDRY_MATCH_DI4 Error Matching Line
Start with Line End for VC4 and DT4 (cleared on read)
Bit 3 – ERR_L_BNDRY_MATCH_DI3 Error Matching Line Start with Line End for VC3 and DT3 (cleared
on read)
Bit 2 – ERR_L_BNDRY_MATCH_DI2 Error Matching Line Start with Line End for VC2 and DT2 (cleared
on read)
Bit 1 – ERR_L_BNDRY_MATCH_DI1 Error Matching Line Start with Line End for VC1 and DT1 (cleared
on read)
Bit 0 – ERR_L_BNDRY_MATCH_DI0 Error Matching Line Start
with Line End for VC0 and DT0 (cleared on read)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
