2.1.1.5 Synchronous Pipeline Register Reset

Each pipeline register has one synchronous reset. In dual-port mode, A_DOUT_SRST_N and B_DOUT_SRST_N drive the synchronous reset of the data output pipeline registers—A_DOUT and B_DOUT. If the synchronous pipeline reset is low, the pipeline data output registers are reset to zero on the next valid clock edge, as shown in the following figure.