2.1.1.7 Read Operation

In dual-port mode, LSRAM supports both pipelined and non-pipelined read operations. In a pipelined read operation, the output data is registered at the pipeline registers; as a result the data is available on the corresponding data output on the next clock cycle.

In a non-pipelined read operation, the pipeline registers are bypassed and read data is available on the output port in the same clock cycle.

Important:
  • For high-performance designs, It is recommended to use the LSRAM with pipeline mode to meet the design timing constraints.
  • When multiple depth-cascaded blocks are used, A_REN and B_REN ports of Dual-Port SRAM are disabled by the configurator GUI.

The following figure shows the timing for both pipelined and non-pipelined read operations in the Dual-Port mode.

Figure 2-6. Read Operation in Dual-Port Mode