2.2.4.2 μSRAM Configurator
(Ask a Question)The μSRAM configurator is available in the Libero SoC software under Memory & Controllers. Figure 1 shows μSRAM available in the Libero SoC software. The RAM configurator automatically cascades μSRAM blocks to create wider and deeper memories by selecting the most efficient aspect ratio. It also handles the grounding of unused bits. The core configurator supports the generation of memories that have same write/read depth and width. The configurator uses one or more memory blocks to generate a RAM matching the configuration. In addition, it also creates the surrounding cascading logic.
- Cascaded deep. For example, two blocks of 64 x 12 combined to create a 128 x 12.
- Cascaded wide. For example, two blocks of 64 x 12 combined to create a 64 x 24.
- Cascaded wide and deep. For example, four blocks of 64 x 12 combined to create a 128 x 24, in two blocks width-wise by two blocks depth-wise configuration.
Write operations are synchronous for setting up the address and writing the data. The memory write operations are triggered at the rising edge of the clock.
Read operations for setting up the address and reading the data can be either asynchronous or synchronous. An optional pipeline register is available for the read-address to improve the setup. An optional pipeline register is available at the read data to improve the clock-to-output delay. Disabling both the address and read data registers creates the asynchronous mode for read operations. For synchronous read operations, the memory read operations are triggered at the rising edge of the clock.
| Port | Direction | Polarity | Description |
|---|---|---|---|
| CLK | Input | Rising edge | Single clock signal that drives both ports with the same clock. Applicable only when Single clock is selected. |
| BLK_EN | Input | Active high | Read port enable |
| R_ADDR[5:0] | Input | — | Read address |
| R_ADDR_EN | Input | Active high | Read address register enable |
| R_ADDR_SRST_N | Input | Active low | Read address register synchronous reset |
| R_ADDR_ARST_N | Input | Active low | Read address register asynchronous reset |
| R_CLK | Input | Rising edge | Read clock. Applicable only when independent clocks are selected. |
| R_DATA[11:0] | Output | — | Read data |
| R_DATA_EN | Input | Active high | Read data register enable |
| R_DATA_SRST_N | Input | Active low | Read data register synchronous reset |
| R_DATA_ARST_N | Input | Active low | Read data register asynchronous reset |
| W_ADDR[5:0] | Input | — | Write address |
| W_CLK | Input | Rising edge | Write clock. Applicable only when independent clocks are selected. |
| W_EN | Input | Active low | Write enable |
| W_DATA[11:0] | Input | — | Write data |
| ACCESS_BUSY | Output | Active high | Busy signal from SmartDebug |
This section also describes the μSRAM configuration and defines how the signals are connected.
The μSRAM configurator window has three tabs for settings:
- Parameter settings
- Port settings
- Memory Initialization settings