25.10.12 Channel Pattern Match Data Register
CHCTRLAk.ENABLE=1 write protected.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CHPDATk |
| Offset: | 0x7C + k*0x50 [k=0..15] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PIGN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PDAT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PDAT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:24 – PIGN[7:0] Channel Pattern Ignore Value
When in Pattern Terminate Mode, any byte matching these bits during a pattern match may be ignored during the pattern match determination when PIGNEN is set. If a byte is read that is identical to this data byte the pattern match logic will treat it as a don’t care when the pattern matching logic is enabled and PIGNEN bit is set.
Bits 15:0 – PDAT[15:0] Channel Pattern Match Data
Channel pattern match data to terminate the ongoing block transfer or linked-list.
PDAT[15:8] (the second byte of data, if enabled by PATLEN == 1) and PDAT[7:0] (the first byte of data) are to be matched with transferred data in order to allow terminate block transfer or linked-list.