25.10.1 Channel Control A Register

Table 25-15. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CHCTRLAk
Offset: 0x50 + k*0x50 [k=0..15]
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
        RUNSTDBY 
Access R/W 
Reset 0 
Bit 2322212019181716 
        SWFRC 
Access W 
Reset 0 
Bit 15141312111098 
        LLEN 
Access R/W/HC 
Reset 0 
Bit 76543210 
        ENABLE 
Access R/W/HC 
Reset 0 

Bit 24 – RUNSTDBY Run in Standby

This bit is used to keep the DMA channel running in standby mode:

ValueDescription
0The channel is halted in standby.
1The channel continues to run in standby. Continue module operation in idle/sleep mode.

Bit 16 – SWFRC Software Force Trigger

Write to 1 to issue a start trigger to the channel. Reading this bit always returns 0.

Bit 8 – LLEN Linked List Enable

ValueDescription
0
1DMA will load the next descriptor at address location to by CHNXTk.NXT[31:0] on completion of the current block transfer or if the channel is idle (i.e. CHCTRLAk.ENABLE=0 and CHSTATk.BLK-BUSY=0). If CHNXTk.NXT[31:0] = 0xFFFF_FFFF (NULL) the DMA will set the CHINTFk.LL status bit and clear LLEN. No further action takes place.

Bit 0 – ENABLE Channel Enable

Writing a 1 to ENABLE enables a block transfer. Upon completion or abort of the block transfer the DMA clears ENABLE.

ValueDescription
0Disable channel block transfers or suspend block transfer if CHSTATk.BLKBUSY=1.
1Block transfer enabled. The DMA will initiate a block transfer on the start trigger selected by CHCTRLBk.TRIG or a software trigger, CHCTRLAk.SWFRC=1.