25.10.6 Channel Interrupt Flag Register
Note: Interrupt flags must be cleared and then read back to confirm the clear before
exiting the ISR to avoid double interrupts.
Reset: This channel resets on a channel reset.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CHINTFk |
| Offset: | 0x60 + k*0x50 [k=0..15] |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RDE | WRE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WRELL | BH | BC | CC | TA | SD | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 18 – RDE Read Error Flag
Write a 1 to this bit to clear the interrupt flag.
| Value | Description |
|---|---|
| 0 | No read bus errors detected |
| 1 | The last read request returned a bus error. The DMA will also clear CHCTRLAk.ENABLE and LLEN on a read error. |
Bit 17 – WRE Write Error Flag
Write a 1 to this bit to clear the interrupt flag.
| Value | Description |
|---|---|
| 0 | No read bus errors detected |
| 1 | The last write request returned a bus error. The DMA will also clear CHCTRLAk.ENABLE and LLEN on a write error. |
Bit 5 – WRELL Linked List Done Interrupt Flag
Write a 1 to this bit to clear the interrupt flag.
| Value | Description |
|---|---|
| 0 | No interrupt is enabled |
| 1 | Linked-List competed, NULL pointer encountered in CHNXTk.NXT when attempting to load the next descriptor and all data from the current block transfer has completed. |
Bit 4 – BH Block Transfer Half Complete Interrupt Flag
Write a 1 to this bit to clear the interrupt flag.
| Value | Description |
|---|---|
| 0 | No interrupt is enabled |
| 1 | Half of the block transfer has completed. |
Bit 3 – BC Block Transfer Complete Interrupt Flag
Write a 1 to this bit to clear the interrupt flag.
| Value | Description |
|---|---|
| 0 | No interrupt is enabled |
| 1 | A block transfer has been completed. |
Bit 2 – CC Cell Transfer Complete Interrupt Flag
Write a 1 to this bit to clear the interrupt flag.
| Value | Description |
|---|---|
| 0 | No interrupt is enabled |
| 1 | A cell transfer has been completed (CSZ bytes has been transferred). |
Bit 1 – TA Transfer Abort Interrupt Flag
Write a 1 to this bit to clear the interrupt flag.
| Value | Description |
|---|---|
| 0 | No interrupt is enabled |
| 1 | An abort trigger event has been detected and the DMA transfer has been aborted. The DMA will also clear CHCTRLAk.ENABLE on a TA event. |
Bit 0 – SD Start Detected Interrupt Flag
Write a 1 to this bit to set the interrupt enable.
| Value | Description |
|---|---|
| 0 | No interrupt is enabled |
| 1 | A start trigger event has been detected and the block transfer has started |