25.10.17 Channel Status Block Count Register

Offset is k=0..DMA_CH_N-1)
Table 25-31. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CHSTATBCk
Offset: 0x90 + k*0x50 [k=0..15]
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        BBTC[16] 
Access R/W 
Reset 0 
Bit 15141312111098 
 BBTC[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 BBTC[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 16:0 – BBTC[16:0] Bytes Transferred in the Block Counter

Reports the number of bytes transferred in the block.

0x10000 = 65,536 bytes transferred

0x00001 = 1 bytes transferred

0x00000 = 0 bytes transferred