25.7.3.7 Block Transfer Enable

The CHCTRLAk.ENABLE bit controls the channel’s ability to perform a block transfer. Setting the bit to 1, either by software or through the linked-list descriptor (see Linked List for details on linked-list operation) notifies DMA FSM that the channel is configured and a start trigger event shall initiate a transfer. On completion or abort of a block transfer, the DMA will always clear CHCTRLAk.ENABLE.

If software clears CHCTRLAk.ENABLE during a block transfer, and a block transfer is in progress (CHSTATk.BLKBUSY=1), the channel suspends the transfer. The CHCTRLAk.ENABLE bit will reflect the written state. When suspended, no new bus requests are issued for the channel and all trigger events are ignored. Setting CHCTRLAk.ENABLE to 1 after suspending resumes the transfer. If CHSTATk.CELLBUSY=1, the current cell transfer resumes. If any of the control registers are modified when suspended, the channel cancels the current block transfer and resets. Channel reset consists of clearing all the status bits, resetting counters to zero, and flushing the channel FIFO. The CHSTATk.BLKBUSY clears at the completion of the channel reset sequence.