25.7.3.10 Pattern Match Termination

Pattern match allows the user to end a block transfer if bytes of data read during a transaction matches a specific pattern, as defined by the PDATA register. Upon the detection of the pattern, an abort trigger is sent to the channel. Any bytes following the pattern match will not be written to the destination. The CHCTRLBk.PATEN enables the pattern detection abort function. Pattern matching is independent of where the data pattern starts in the byte stream of the source data. Pattern matching is always performed in the original order in which data was read, therefore CHCTRLBk.BYTORD[1:0] does not affect pattern matching.

Since pattern matching operates on a byte boundary, if the WAS alignment is set to a halfword or fixed word, the DMA may perform a byte wide write on the last transaction depending on where the pattern match is detected.

Byte Ignore

When two-byte pattern detect is enabled and the ignore byte is also enabled, any read data byte encountered that has the same bit pattern as the CHPDATk.PIGN[7:0] data field will be treated as a don’t care during the pattern matching process. The read data will still be transferred; it just will be ignored when attempting to determine a pattern match. When CHCTRLBk.PIGNEN=0 the CHPDATk.PIGN[7:0] has no effect on pattern matching.

Note: When PIGNEN=1 the user should ensure that the byte held in PIGN for that channel is not the same as any byte(s) specified in PDATA that is participating in the pattern match.

Pattern Matching

When the Pattern is only a single byte in length the first byte in the read data that matches is a pattern match. Any valid bytes following the pattern match in the read data shall not be written. The read data up to and including the pattern match is placed in the channel FIFO, and further reads for that channel cease. When all the data in the FIFO is written out to the destination, the DMA clears CHCTRLAk.ENABLE and sets the appropriate interrupt flags as described in Abort Trigger Source.

When the Pattern consists of two bytes, a match requires a read byte to match the value in CHPDATk.PDAT[7:0] and the next read byte to match CHPDATk.PDAT[15:8]. If CHCTRLBk.PIGNEN=1 then the two matched bytes may be separated by any number of don’t care bytes as defined by CHPDATk.PIGN[7:0]. Any read bytes following the pattern match are not written out to the destination. The read data up to the final byte of the pattern match is placed in the channel FIFO, further reads for that channel cease, When all the data in the FIFO is written out to the destination, the DMA clears CHCTRLAk.ENABLE and sets the appropriate interrupt flags as described in Abort Trigger Source.

Bytes matching the pattern may be spread over multiple consecutive reads for a channel and must be treated as a contiguous stream.

Consider as a pattern match example a two byte pattern that is to match on CR and LF. The option of ignoring null characters could be considered by setting PIGN to zero and enabling the ignore feature with PIGNEN=1. This way, when a CR character occurs followed by 0 or more null characters and then followed by a LF character occurs, the match is detected when the LF character is encountered.

In either case bytes that have been read that follow the matching pattern will not be part of the final data transaction. Pattern matching occurs before any output data reordering.

Note: A pattern match may only occur within the limits of the transfer of data as described by a linked list descriptor. The pattern match may not span across descriptor transfers.

Pattern Match Example

Assuming a system that has a series of messages that are routinely transmitted to an external host through the UART. Assuming a maximum message size of 86 characters. The user would set the following parameters on the channel:

  • Source Start Address is set to the start of the message
  • Destination Start Address is set to the UART transmit FIFO
  • Block Transfer Size is set to 86 bytes
  • Cell Transfer Size is set to 1/2 the UART transmit FIFO depth.
  • Source Cell Stride Size is set to the Cell Transfer Size
  • Destination Cell Stride Size is ignored due to the Fixed Address mode setting for the destination.
  • Read Address Sequence Mode is set to Increment Address / Auto
  • Write Address Sequence Mode is set to Fixed Address / Byte. This assumes the UART transmit FIFO can only accept a single byte per write.
  • Start trigger event source is set to the UART DMA transmit request which asserts when the UART transmit FIFO is half full.
  • The channel is configured to accept a pattern match abort, CHCTRLBk.PATEN=1, of a single byte length pattern, CHCTRLBk.PATLEN=0, of 0x00, CHPDATk.PDAT[7:0] = 0x00.

Once CHCTRLAk.ENABLE is set to 1, the DMA will transfer data to the UART based on the UART DMA request for data until the 0x00 byte pattern is detected.

Note: The pattern match bytes and don’t care bytes are always written to the destination.