25.7.3.12 Bus Error Handling

If a channel receives a bus error for a read or write request, the DMA will clear the CHCTRLAk.ENABLE and CHCTRLAk.LLEN fields to disable the channel. The status bits in CHSTATk are cleared when all pending transactions complete. For an error on the DMAR port, the DMA sets the CHINTFk.RDE interrupt flag and issues an interrupt. For an error on the DMAW port, the DMA sets the CHINTFk.WRE interrupt flag and issues an interrupt. The interrupt flags are set after clearing the status bits in CHSTATk.