25.7.3.1 Address Sequence and Transfer Modes
The address sequence mode which is individually programmable for the source and destination, determines how the DMA calculates the read and write addresses and the amount of data that can be transferred in a single bus transaction (beat). The CHCTRLBk.RAS[2:0] register field sets the address sequence mode for source reads. The CHCTRLBk.WAS[2:0] register field sets the address sequence mode for the destination writes.
There are two address modes that are supported, fixed address and increment address. In fixed address mode, the address does not increment between consecutive transactions. In increment address mode, the address increments based on the number of bytes transferred per beat.
The following address and byte transfer combinations are supported
- Fixed Address / Byte transfer
- Fixed Address / Half word transfer
- Fixed Address / Word transfer
- Increment Address / Byte transfer
- Increment Address / Half word transfer
- Increment Address / Auto transfer size
In Fixed Address/ Byte transfer mode the address is fixed to the start address (see Source Start Address and Destination Start Address for a start address definition) with no address alignment restrictions. Read or write beats are of byte length. Use this address sequence mode to read or write a peripheral FIFO with byte wide access. Similarly, in Fixed Address / Half word mode, the address is fixed to the start address which must be half word aligned. Read or write beats are two bytes wide. In Fixed Address / Word mode the address is fixed to the start address and must be aligned to a word boundary. Read or write beats are 4 bytes wide. The DMA is capable of bursting up to 4 beats to improve bus traffic efficiency in Fixed Address / Word mode.
In Increment Address / Byte transfer mode the read or write address increments by one byte after each beat, beginning at the start address. In Increment Address / Half word transfer mode the read or write address increments by two bytes after each beat, beginning at the start address. The start address must be half word aligned. In Increment Address/ Auto transfer mode, the beat size and address increment amount are determined by the DMA to optimally read or write data. If the start address is aligned to the interface data width (64 bits) and the block and cell transfer sizes are also aligned to the interface data width, all beats in this mode are the width of interface and bursts of up to 4 beats are possible.
For an example of the Increment Address/ Auto, consider a data packet of 64 bytes in memory starting at address 0x0000_0001, The data packet needs to be copied into a communication peripheral’s FIFO which can accept word writes and can hold 16 bytes of data at one time. The Source Start Address is set to 0x0000_0001. The Destination Start Address is set to the FIFO register location which is on a word boundary. The Block Transfer Size is set to the packet size of 64 bytes. The Cell Transfer Size is set to 8 bytes, which is half of the FIFO’s capacity. The Read Address Sequence is set to Increment Address / Auto and the Write Address Sequence is set to Fixed Address / Word. The interface data width is 32-bits wide. The channel is programed to trigger a cell transfer when the peripheral FIFO is less than half full.
On the first trigger, the DMA will issue a single byte read starting at 0x0000_0001, a half-word read at 0x0000_0002, followed by a full word read, and finally a single byte read at 0x0000_0008. In the channel FIFO, the DMA realigns data to match the beat size of the data word. Two words are burst out using fixed address set by the Destination Start Address. At this point the DMA will wait for another trigger event from the peripheral before transferring another cell. Cell transfers continue until a block transfer completes.