1.3 SmartHLS™ 2024.1

Release Date: February, 2024

Software Features and Enhancements

  • New open-source SmartHLS™ Fixed-Point Math Library hosted on Github:
    • Comprehensive suite of configurable trigonometric and transcendental functions.
    • Practical usage examples, detailed documentation, resource usage reports, and error plots.
    • New gdb pretty-printer for ap_[u]fixpt data types.
  • Optimized wide-multiplication with significant improvements to latency and resources usage. The new optimization offers two modes:
    • Default mode:
      • Optimizes for latency and Logic Elements (LEs).
      • For a 128x128 pipelined multiplier with 200MHz target FMax, the latency is reduced by 6X and LEs are reduced by ~2X compared to SmartHLS 2023.2 as shown in Table 1-1.
    • Min-math mode:
      • Optimizes math blocks usage with up to 50% reduction (depending on the multiplication size) compared to the default mode.
      • For a 128x128 pipelined multiplier with 200MHz target FMax, the math blocks usage is reduced by 44% with only 1 cycle increase in latency and ~10% increase in LEs compared to the default mode as shown in Table 1-1.
      • Min-math wide-multiplication mode can be activated using the new MINIMIZE_MATH_BLOCKS Tcl command.
    Table 1-1. 128x128 Pipelined Multiplier (Target FMax = 200MHz)
    SmartHLS™ VersionLatencyFMaxMathLUTsDFFsLEs
    2023.236267.16428231307313085
    2024.1Default6251.264589037946201
    Min-math7237.336674237526930
  • Introduced support for RTG4™ devices.
  • New high-reliability and RTL synthesis options:
  • Updates to dependencies included with SmartHLS installer:
    • A math and vision library snapshot included with installer.
    • OpenCV/FFMPEG precompiled software libraries are now included with SmartHLS.
    • Cygwin dependency removed from Windows installation, which results in 4X faster shls execution.
    • Software compile/run (shls sw) now uses the MinGW-w64 GCC compiler instead of the Cygwin GCC compiler.
  • The SmartHLS project Makefile now only supports a subset of Makefile syntax (see 3.5.1.31 HLS Makefile for details).
  • Coding style of the synthesized Verilog design improved.
  • Several improvements to bit-width minimization, delay modeling, pipelining and dataflow.
  • Robustness of the C++ Arbitrary Data Types Library improved.
  • Removed fence.i instructions from driver code generated for HLS modules when used with MIV_RV32 system (following Section 3.7.1 in MIV_RV32 Migration Guide). On MIV_RV32, the fence.i instruction is treated as a NOP and causes a five-cycle delay in decoding.
  • Wide range of OS support: Windows 10, Windows 11, Ubuntu 18.04, Ubuntu22.04, CentOS7 and CentOS8.

Resolved Issues

  • Number of Place & Route passes set to 1 by default instead of 25 to avoid long RTL synthesis (can be overridden using NUM_LIBERO_PnR_PASSES Makefile variable).
  • The default inference of constant global variables used by both hardware and testbench changed to local memory instead of an interface. Memory interface pragma can be used to change the default behavior.
  • Global variable initialization for struct/class types with complex constructors is now supported.
  • Right-shift operation for signed Arbitrary Precision Data Types changed to arithmetic shift. lshr can be used for right logical shift.

Known Issues

  • Pipelining a nested loop will always unroll the inner loops. This can significantly increase the outer loop body and causes the compiler to crash. To avoid this issue, use loop pipelining for the inner loops for these cases.
  • Dataflow function ready signal will wait for sub-functions accessing non-FIFO external memories. This can lead in degradation in performance. To avoid this issue, use FIFOs instead for input and output interfaces.
  • When you right click on an active project and select Build Project from the context menu that appears, the build will fail with the following error. To avoid this issue, use the SmartHLS build buttons or the SmartHLS menu bar to build the project.
    Error: More than one target specified: C:\Developers\latest_windows_Libero_SoC\SmartHLS-2024.1\SmartHLS\bin\shls.bat hw
please specify one target only, or use '-s' option to skip running all prerequisite steps.
  • On Windows 11, some Libero output log messages are trimmed or appear missing from the SmartHLS IDE Console Message tab when you synthesize the circuit using the Synthesize Hardware to FPGA icon in the SmartHLS IDE menu bar. To avoid this issue, open the generated SmartHLS report available at hls_output/reports/summary.results.rpt for the given project to view the timing, resource, and simulation results of the top module. You can also find the Libero project with associated log files at hls_output/synthesis/<top>.
  • You see red wavy lines and "Function could not be resolved" errors in the SmartHLS IDE. To address this issue, select Project > C/C++ Index > Rebuild on the SmartHLS IDE menu bar and wait until the index is rebuilt. The red lines will disappear.