3.6.2.4.24 SYNTHESIS_FSM_ENCODING
(Ask a Question)This constraint allows users override the default finite state machine encoding chosen by the synthesis tools with the specified encoding style.
The style string value specified in this parameter will be used to generate a Synopsys synthesis attribute for each state machine register in the compiled design.
- Category
- HLS Constraints
- Value Type
- String
- Valid Values
"onehot","gray","sequential","safe","original"and combination of multiple valid values separated by comma.- Default Values
- "onehot"
- Location Where Default is Specified
examples/legup.tcl- Dependencies
- None
- Applicable Flows
- All devices and flows
- Test Status
- Actively in-use
- Examples
set_parameter SYNTHESIS_FSM_ENCODING "onehot,safe"Synthesis attribute for the state machine register will be generated at the output Verilog code, as follows.
reg [`W-1:0] cur_state /* synthesis syn_encoding="onehot,safe" */;