5.4 Creating and Verifying Designs

Using the Export Component Description option, you can export components such as SmartDesign components, configured cores, and HDL+ cores separately as Tcl.

To export a SmartDesign component:

1. Right-click the component and choose Export Component Description (Tcl).

2. Click the Browse button to specify the location where you want to export the Tcl file, and then click OK.

This option exports the complete design and its subcomponents to Tcl. When this option is executed on a SmartDesign, it iterates through all the instances and collects information about the pins, groups, and nets in the SmartDesign. All the TCL scripts generated are exported to a folder you select when the Hierarchical Export Component Description (Tcl) option executes.

To run this option, right-click the desired component for which the information must be exported in Tcl in the Design/ Stimulus Hierarchy, and then choose Hierarchical Export Component Description (Tcl).

Hierarchical Export Component Description (Tcl) support is not available for blocks.

The following table lists the messages that the tool generates in the log window.

Before your SmartDesign component can be used by downstream processes, such as synthesis and simulation, you must generate it.

Click the Generate

Generating a SmartDesign component might fail if there are any design rule checking (DRC) errors. DRC errors must be corrected before you generate your SmartDesign design.

If the ports of a sub-design change, the parent SmartDesign component is annotated with the icon

You can generate a SmartDesign component recursively or nonrecursively. These options are set in the Project Preference Dialog Box - Design Flow Preferences section.

Table 5-22. Design Flow Preferences Options

Option	Description
Recursive generation	Clicking the Generate button generates all sub-design SmartDesigns, depth first. The parent SmartDesign is generated only if all the sub-designs generate successfully.
Non-Recursive generation	Clicking the Generate button generates the specified SmartDesign only. The generation can be marked as successful even if a sub-design is “ungenerated” (either never attempted or unsuccessful). An ungenerated component is annotated with the icon in the Design Hierarchy tab of the Design Explorer.

To create a core from your HDL:

1. Import or create a new HDL source file; the HDL file appears in the Design Hierarchy.
2. Select the HDL file in the Design Hierarchy and click the HDL+ icon.

   or

   Right-click the HDL file and choose Create Core from HDL.

   The Edit Core Definition – Ports and Parameters dialog box shows the ports and parameters that were extracted from your HDL module.

3. Remove parameters that are not intended to be configurable by selecting them from the list and clicking the X icon. Remove parameters that are used for internal variables, such as state machine enumerations. If you remove a parameter by accident, click Re-extract ports and parameters from HDL file to reset the list so it matches your HDL module.

   

4. (Optional) To add bus interfaces to your core, click Add/Edit Bus Interfaces.
5. After you specify the information, your HDL turns into an HDL+ icon in the Design Hierarchy. Click and drag your HDL+ module from the Design Hierarchy to the Canvas.
6. If you added bus interfaces to your HDL+ core, it appears in your SmartDesign, with a bus interface pin you can use to connect to the appropriate bus IP core.
7. If your HDL+ has configurable parameters, double-click the object on the Canvas (or right-click and choose Configure) to set the values. On generation, the specific configuration values per instance are written to the SmartDesign netlist.

   

8. To open the HDL file inside the text editor, right-click the instance and choose Modify HDL.

After you create a core definition, you can edit it by selecting your HDL+ module in the Design Hierarchy and clicking the HDL+ icon.

Create HDL opens the HDL editor with a new VHDL or Verilog file. Your new HDL file is saved to your /hdl directory and all modules created in the file appear in the Design Hierarchy.

You can use VHDL and Verilog to implement your design.

To create an HDL file:

1. In the Design Flow window, double-click Create HDL. The Create new HDL file dialog box opens.
2. Select your HDL Type. Choose whether to Initialize file with standard template to populate your file with default headers and footers. The HDL Editor workspace opens.
3. Enter a name. Do not enter a file extension because Libero SoC adds one for you. The filename must follow Verilog or VHDL file naming conventions.
4. Click OK.
5. After creating your HDL file, click the Save button to save your file to the project.

The HDL Editor is a text editor for editing HDL source files. In addition to regular editing features, the editor provides keyword highlighting, line numbering, and a syntax checker.

You can have multiple files open at one time in the HDL Editor workspace. Click the tabs to move between files.

To start the editor:

The HDL syntax checker parses through HDL files to identify typographical mistakes and syntactical errors.

To run the syntax checker:

1. From the Files list, double-click the HDL file to open it.
2. Right-click in the body of the HDL editor and choose Check HDL File. The syntax checker parses the selected HDL file and looks for typographical mistakes and syntactical errors. Warnings and error messages for the HDL file appear in the Libero SoC Log window.

You can comment text as you type in the HDL Editor, or you can comment out blocks of text by selecting a group of text and applying the Comment command.

To comment or uncomment out text:

1. Type your text.
2. Select the text.
3. Right-click inside the editor and choose Comment Selection or Uncomment Selection.

You can search for a whole or partial word, with or without matching the case.

To find an entire or partial word:

1. From the File menu, choose Find. The Find dialog box appears below the Log/Message window.
2. Enter the text you want to find.
3. Use the options to match case, whole word, and/or regular expression.

To select a column of text to edit, select the column, and then press ALT+Click.

To import an HDL source file:

1. In the Design Flow window, right-click Create HDL and choose Import Files. The Import Files window appears.
2. Go to the location where the HDL file is located.
3. Select the file to import and click Open.
   Note: You can import SystemVerilog (*.sv), Verilog (*.v), and VHDL (*.vhd/*.vhdl) files.

When you create a new project, you select a preferred language. The HDL files generated in the flow are created in the preferred language. If your preferred language is Verilog, the post-synthesis and post-layout netlists are in Verilog 2001.

The language used for simulation is the same language as the last compiled testbench. For example, if tb_top is in Verilog, <fam>.v is compiled.

Set HDL Type to Verilog or VHDL for the testbench.

Specify a testbench file name. A *.v or a *.vhd file is created and opened in the HDL Editor.

Enter a clock period in nanoseconds (ns) for the clock to drive the simulation. The default value is 100 ns (10 MHz). Libero creates in the testbench a SYSCLK signal with the specified frequency to drive the simulation.

The Project Settings dialog box allows you to change how Libero SoC handles DO files in simulation and imports your DO files. You can also set simulation run time, change the DUT name used in your simulation, and change your library mapping.

To access the Project Settings dialog box:

1. From the Project menu, choose Project Settings.
2. In the left pane, click Simulation options or Simulation libraries to expand the options.
3. For Simulation options, click the option you want to edit:
   • DO file
   • Waveforms
   • Vsim commands
   • Timescale
4. For Simulation libraries, click the library whose path you want to change.

Before running simulation, associate a testbench. If you try to run simulation without an associated testbench, the Libero SoC Project Manager prompts you to associate a testbench or open ModelSim without a testbench.

To associate a stimulus:

1. Run the simulation.

   or

   In the Design Flow window, under Verify Pre-Synthesized Design, right-click Simulate and choose Organize Input Files > Organize Stimulus Files.

   The Organize Stimulus Files dialog box appears.
2. Associate your testbenches. In the Organize Stimulus Files dialog box, all the stimulus files in the current project appear in Source Files in the Project list box. Files already associated with the block appear in the Associated Source Files list box.

   In most cases, you will have one testbench associated with your block. However, if you want simultaneous association of multiple testbench files for one simulation session, as in the case of PCI cores, add multiple files to the Associated Source Files list.

   • To add a testbench: Select the testbench you want to associate with the block in Source Files in the Project list box and click Add to add it to the Associated Source Files list.
   • To remove a testbench or change the files in the Associated Source Files list box: Select the files and click Remove.
   • To order testbenches: Use the up and down arrows to arrange the order in which you want the testbenches compiled. The top level-entity must be at the bottom of the list.
3. When you are satisfied with the Associated Source Files list, click OK.

Libero SoC passes all the source files related to the top-level module to simulation.

If you need additional modules in simulation:

To perform functional simulation:

1. Create your testbench.
2. In the Design Flow window, select Implement Design > Verify Post-Synthesis Implementation.
3. Right-click Simulate and choose Organize Input Files > Organize Simulation Files from the right-click menu. In the Organize Files for Source dialog box, all the stimulus files in the current project appear under Source Files in the Project list box. Files associated with the block appear in the Associated Source Files list box.
4. In most cases, you will have one testbench associated with your block. However, if you want simultaneous association of multiple testbench files for one simulation session, as in the case of PCI cores, add multiple files to the Associated Source Files list.
   • To add a testbench: In the Source Files of the Project list box, select the testbench you want to associate with the block. Click Add to add it to the Associated Source Files list.
   • To remove a testbench or change the files in the Associated Source Files list box: Select the files and click Remove.
5. When you are satisfied with the Associated Simulation Files list, click OK.
6. To start ModelSim ME Pro, right-click Simulate in the Design Hierarchy window and choose Open Interactively. ModelSim starts and compiles the appropriate source files. When the compilation completes, the simulator runs for 1̮ ms and the Wave window shows the simulation results.
7. Scroll in the Wave window to verify that the logic of your design functions as intended. Use the zoom buttons to zoom in and out as necessary.
8. When finished, select Quit from the File menu.