50.28 I2C Bus Data Requirements

Table 50-26. **I²C Bus Data Requirements**
Standard Operating Conditions (unless otherwise stated)
SP100*	T_HIGH	Clock high time	100 kHz mode	4000	—	ns	Device must operate at a minimum of 1.5 MHz
SP100A*	400 kHz mode	600	—	ns	Device must operate at a minimum of 10 MHz
SP100B*	1 MHz mode	260	—	ns	Device must operate at a minimum of 10 MHz
SP101*	T_LOW	Clock low time	100 kHz mode	4700	—	ns	Device must operate at a minimum of 1.5 MHz
SP101A*	400 kHz mode	1300	—	ns	Device must operate at a minimum of 10 MHz
SP101B*	1 MHz mode	500	—	ns	Device must operate at a minimum of 10 MHz
SP102*	T_R	SDA and SCL rise time	100 kHz mode	—	1000	ns
SP102A*	400 kHz mode	20	300	ns	C_B is specified to be from 10-400 pF
SP102B*	1 MHz mode	—	120
SP103*	T_F	SDA and SCL fall time	100 kHz mode	—	250	ns
SP103A*	400 kHz mode	20 × (V_DD/5.5V)	250	ns	C_B is specified to be from 10-400 pF
SP103B*	1 MHz mode	20 × (V_DD/5.5V)	120	ns
SP106*	T_HD:DAT	Data input hold time	100 kHz mode	0	—	ns
SP106A*	400 kHz mode	0	—	ns
SP106B*	1 MHz mode	0	—	ns
SP107*	T_SU:DAT	Data input setup time	100 kHz mode	250	—	ns	(Note 2)
SP107A*	400 kHz mode	100	—	ns
SP107B*	1 MHz mode	50	—	ns
SP109*	T_AA	Output valid from clock	100 kHz mode	—	3450	ns	(Note 1)
SP109A*	400 kHz mode	—	900	ns
SP109B*	1 MHz mode		450	ns
SP110*	T_BUF	Bus free time	100 kHz mode	4700	—	ns	Time the bus must be free before a new transmission can start
SP110A*	400 kHz mode	1300	—	ns
SP110B*	1 MHz mode	500	—	ns
SP111	C_B	Bus capacitive loading	100 kHz mode	—	400	pF
SP111A	400 kHz mode	—	400	pF
SP111B	1 MHz mode	—	26	pF
SP112	C_I	Capacitance for each I/O pin	—	—	10	pF
* These parameters are characterized but not tested. Note: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the requirement T_SU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + T_SU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification), before the SCL line is released.

SP100*

T_HIGH

Clock high time

100 kHz mode

4000

—

ns

Device must operate at a minimum of 1.5 MHz

SP100A*

400 kHz mode

600

—

ns

Device must operate at a minimum of 10 MHz

SP100B*

1 MHz mode

260

—

ns

Device must operate at a minimum of 10 MHz

SP101*

T_LOW

Clock low time

100 kHz mode

4700

—

ns

Device must operate at a minimum of 1.5 MHz

SP101A*

400 kHz mode

1300

—

ns

Device must operate at a minimum of 10 MHz

SP101B*

1 MHz mode

500

—

ns

Device must operate at a minimum of 10 MHz

SP102*

T_R

SDA and SCL rise time

100 kHz mode

—

1000

ns

SP102A*

400 kHz mode

20

300

ns

C_B is specified to be from 10-400 pF

SP102B*

1 MHz mode

—

120

SP103*

T_F

SDA and SCL fall time

100 kHz mode

—

250

ns

SP103A*

400 kHz mode

20 × (V_DD/5.5V)

250

ns

C_B is specified to be from 10-400 pF

SP103B*

1 MHz mode

20 × (V_DD/5.5V)

120

ns

SP106*

T_HD:DAT

Data input hold time

100 kHz mode

0

—

ns

SP106A*

400 kHz mode

0

—

ns

SP106B*

1 MHz mode

0

—

ns

SP107*

T_SU:DAT

Data input setup time

100 kHz mode

250

—

ns

(Note 2)

SP107A*

400 kHz mode

100

—

ns

SP107B*

1 MHz mode

50

—

ns

SP109*

T_AA

Output valid from clock

100 kHz mode

—

3450

ns

(Note 1)

SP109A*

400 kHz mode

—

900

ns

SP109B*

1 MHz mode

450

ns

SP110*

T_BUF

Bus free time

100 kHz mode

4700

—

ns

Time the bus must be free before a new transmission can start

SP110A*

400 kHz mode

1300

—

ns

SP110B*

1 MHz mode

500

—

ns

SP111

C_B

Bus capacitive loading

100 kHz mode

—

400

pF

SP111A

400 kHz mode

—

400

pF

SP111B

1 MHz mode

—

26

pF

SP112

C_I

Capacitance for each I/O pin

—

10

pF

* These parameters are characterized but not tested.

Note:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the requirement T_SU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + T_SU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification), before the SCL line is released.

Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Characteristic		Min.	Max.	Units	Conditions
SP100*	T_HIGH	Clock high time	100 kHz mode	4000	—	ns	Device must operate at a minimum of 1.5 MHz
SP100A*			400 kHz mode	600	—	ns	Device must operate at a minimum of 10 MHz
SP100B*			1 MHz mode	260	—	ns	Device must operate at a minimum of 10 MHz
SP101*	T_LOW	Clock low time	100 kHz mode	4700	—	ns	Device must operate at a minimum of 1.5 MHz
SP101A*			400 kHz mode	1300	—	ns	Device must operate at a minimum of 10 MHz
SP101B*			1 MHz mode	500	—	ns	Device must operate at a minimum of 10 MHz
SP102*	T_R	SDA and SCL rise time	100 kHz mode	—	1000	ns
SP102A*			400 kHz mode	20	300	ns	C_B is specified to be from 10-400 pF
SP102B*			1 MHz mode	—	120
SP103*	T_F	SDA and SCL fall time	100 kHz mode	—	250	ns
SP103A*			400 kHz mode	20 × (V_DD/5.5V)	250	ns	C_B is specified to be from 10-400 pF
SP103B*			1 MHz mode	20 × (V_DD/5.5V)	120	ns
SP106*	T_HD:DAT	Data input hold time	100 kHz mode	0	—	ns
SP106A*			400 kHz mode	0	—	ns
SP106B*			1 MHz mode	0	—	ns
SP107*	T_SU:DAT	Data input setup time	100 kHz mode	250	—	ns	(Note 2)
SP107A*			400 kHz mode	100	—	ns
SP107B*			1 MHz mode	50	—	ns
SP109*	T_AA	Output valid from clock	100 kHz mode	—	3450	ns	(Note 1)
SP109A*			400 kHz mode	—	900	ns
SP109B*			1 MHz mode		450	ns
SP110*	T_BUF	Bus free time	100 kHz mode	4700	—	ns	Time the bus must be free before a new transmission can start
SP110A*			400 kHz mode	1300	—	ns
SP110B*			1 MHz mode	500	—	ns
SP111	C_B	Bus capacitive loading	100 kHz mode	—	400	pF
SP111A			400 kHz mode	—	400	pF
SP111B			1 MHz mode	—	26	pF
SP112	C_I	Capacitance for each I/O pin	—	—	10	pF
* These parameters are characterized but not tested. Note: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the requirement T_SU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + T_SU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification), before the SCL line is released.