38.11.3 ADCCON2 – ADC Control Register 2
This register controls the reference selection for the ADC module, the sample time for the shared ADC module, interrupt enable for reference, early interrupt selection and clock division selection for the shared ADC.
Name: | ADCCON2 |
Offset: | 0x1410 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
BGVRRDY | REFFLT | EOSRDY | SAMC[9:8] | ||||||
Access | R/HS/HC | R/HS/HC | R/HS/HC | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
SAMC[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
BGVRIEN | REFFLTIEN | EOSIEN | ENXCNVRT | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ADCDIV[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – BGVRRDY Band Gap Voltage/ADC Reference Voltage Status bit
Data processing is valid only after BGVRRDY is set by hardware, so the application code must check that the BGVRRDY bit is set to ensure data validity. This bit set to ‘0
’ when ON (ADCCON1[15]) = 0
.
Value | Description |
---|---|
0 | Either or both band gap voltage and ADC reference voltages (VREF) are not ready |
1 | Both band gap voltage and ADC reference voltages (VREF) are ready |
Bit 30 – REFFLT Band Gap/VREF/AVDD BOR Fault Status bit
This bit is cleared when the ON bit (ADCCON1[15]) = 0
and the BGVRRDY bit = 1
.
Value | Description |
---|---|
0 | Band gap and VREF voltage are working properly |
1 | Fault in band gap or the VREF voltage while the ON bit (ADCCON1[15]) was set. Most likely a band gap or VREF fault is caused by a BOR of the analog VDDsupply. |
Bit 29 – EOSRDY End of Scan Interrupt Status bit
This bit is cleared when ADCCON2[31:24] are read in software.
Value | Description |
---|---|
0 | Scanning has not completed |
1 | All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in the ADCCSS1 and ADCCSS2 registers) have completed scanning |
Bits 25:16 – SAMC[9:0] SampleTime for the Shared ADC (ADC2) bits
Where TAD7 = Period of the ADC conversion clock for the Shared ADC (ADC2) controlled by the ADCDIV[6:0] bits.
Value | Description |
---|---|
1111111111 | 1025 TAD7 |
... | |
0000000001 | 3 TAD7 |
0000000000 | 2 TAD7 |
Bit 15 – BGVRIEN Band Gap/VREF Voltage Ready Interrupt Enable bit
Value | Description |
---|---|
0 | No interrupt is generated when the BGVRRDY bit is set |
1 | Interrupt is generated when the BGVRDDY bit is set |
Bit 14 – REFFLTIEN Band Gap/VREF Voltage Fault Interrupt Enable bit
Value | Description |
---|---|
0 | No interrupt is generated when the REFFLT bit is set |
1 | Interrupt is generated when the REFFLT bit is set |
Bit 13 – EOSIEN End of Scan Interrupt Enable bit
Value | Description |
---|---|
0 | No interrupt is generated when the EOSRDY bit is set |
1 | Interrupt is generated when the EOSRDY bit is set |
Bit 11 – ENXCNVRT Enable External Conversion Request Interface
Bits 6:0 – ADCDIV[6:0] Division Ratio for the Shared SAR ADC Core Clock bits
Value | Description |
---|---|
1111111 | 254 * TQ = TAD2 |
... | |
0000011 | 6 * TQ = TAD2 |
0000010 | 4 * TQ = TAD2 |
0000001 | 2 * TQ = TAD2 |
0000000 | Reserved |