38.11.16 ADCTRG2 – ADC Trigger Source 2 Register
This register controls the trigger source selection for AN4 through AN7 analog inputs.
Name: | ADCTRG2 |
Offset: | 0x1610 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
TRGSRC7[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TRGSRC6[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
TRGSRC5[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TRGSRC4[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bits 28:24 – TRGSRC7[4:0] Trigger Source for Conversion of Analog Input AN7 Select bits
Note: For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC[4:0] bits (ADCCON1[20:16]) to select the trigger source, and requires the appropriate CSS bits to be set in the ADCCSSx registers.
Value | Description |
---|---|
10001 - 11111 | Reserved |
10000 | EVSYS_47 |
01111 | EVSYS_46 |
01110 | EVSYS_45 |
01101 | EVSYS_44 |
01100 | EVSYS_43 |
01011 | EVSYS_42 |
01010 | EVSYS_41 |
01001 | EVSYS_40 |
01000 | EVSYS_39 |
00111 | EVSYS_38 |
00110 | EVSYS_37 |
00101 | EVSYS_36 |
00100 | INT0 External interrupt |
00011 | STRIG |
00010 | Global level software trigger (GLSWTRG) |
00001 | Global software edge trigger (GSWTRG) |
00000 | No Trigger |
Bits 20:16 – TRGSRC6[4:0] Trigger Source for Conversion of Analog Input AN6 Select bits
Note: See bits 28-24 for bit value definitions.
Bits 12:8 – TRGSRC5[4:0] Trigger Source for Conversion of Analog Input AN5 Select bits
Note: See bits 28-24 for bit value definitions.
Bits 4:0 – TRGSRC4[4:0] Trigger Source for Conversion of Analog Input AN4 Select bits
Note: See bits 28-24 for bit value definitions.