38.11.17 ADCCMPCON1 – ADC Digital Comparator 1 Control Register
This register controls the operation of Digital Comparator 1, including the generation of interrupts, comparison criteria to be used and provides status when a comparator event occurs.
Name: | ADCCMPCON1 |
Offset: | 0x1680 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
AINID[5:0] | |||||||||
Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ENDCMP | DCMPGIEN | DCMPED | IEBTWN | IEHIHI | IEHILO | IELOHI | IELOLO | ||
Access | R/W | R/W | R/HS/HC | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 13:8 – AINID[5:0] Digital Comparator 1 Analog Input Identification (ID) bits
When a digital comparator event occurs (DCMPED = 1
), these bits identify the analog input being monitored by digital comparator 1.
Value | Description |
---|---|
111111 | Reserved |
... | |
... | |
... | |
101101 | Reserved |
101100 | Reserved |
101011 | Reserved |
000111 | AN7 is being monitored |
... | |
000001 | AN1 is being monitored |
000000 | AN0 is being monitored |
Bit 7 – ENDCMP Digital Comparator 1 Enable bit
Value | Description |
---|---|
1 | Digital comparator 1 is enabled |
0 | Digital comparator 1 is not enabled, and the DCMPED status bit (ADCCMP0CON[5]) is cleared |
Bit 6 – DCMPGIEN Digital Comparator 1 Global Interrupt Enable bit
Value | Description |
---|---|
1 | A Digital comparator 1 interrupt is generated when the DCMPED status bit (ADCCMP0CON[5]) is set |
0 | A Digital comparator 1 interrupt is disabled |
Bit 5 – DCMPED Digital Comparator 1 “Output True” Event Status bit
The logical conditions under which the digital comparator becomes “True” are defined by the IEBTWN, IEHIHI, IEHILO, IELOHI and IELOLO bits.
0
’).Value | Description |
---|---|
1 | Digital comparator 1 output true event has occurred (output of comparator is ‘ |
0 | Digital comparator 1 output is false (output of comparator is ‘ |
Bit 4 – IEBTWN Between Low/High Digital Comparator 1 Event bit
Value | Description |
---|---|
1 | Generate a digital comparator event when DATA[31:0] is less than DCMPHI[15:0] AND greater than DCMPLO[15:0] |
0 | Do not generate a digital comparator event |
Bit 3 – IEHIHI High/High Digital Comparator 1 Event bit
Value | Description |
---|---|
1 | Generate a digital comparator 1 event when DCMPHI[15:0] bits are less than or equal to DATA[31:0] bits |
0 | Do not generate an event |
Bit 2 – IEHILO High/Low Digital Comparator 1 Event bit
Value | Description |
---|---|
1 | Generate a digital comparator 1 event when DATA[31:0] bits are less than DCMPHI[15:0] bits |
0 | Do not generate an event |
Bit 1 – IELOHI Low/High Digital Comparator 1 Event bit
Value | Description |
---|---|
1 | Generate a digital comparator 1 event when DCMPLO[15:0] bits are less than or equal to DATA[31:0] bits |
0 | Do not generate an event |
Bit 0 – IELOLO Low/Low Digital Comparator 1 Event bit
Value | Description |
---|---|
1 | Generate a digital comparator 1 event when DATA[31:0] bits are less than DCMPLO[15:0] bits |
0 | Do not generate an event |