38.11.2 ADCCON1 – ADC Control Register 1
Name: | ADCCON1 |
Offset: | 0x1400 |
Reset: | 0x00601000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
FRACT | SELRES[1:0] | STRGSRC[4:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
ON | FRZ | SIDL | FSYDMA | FSYUPB | SCANEN | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
IRQVS[2:0] | STRGLVL | DMABL[2:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 23 – FRACT Fractional Data Output Format bit
Value | Description |
---|---|
0 | Integer |
1 | Fractional |
Bits 22:21 – SELRES[1:0] Shared ADC (ADC2) Resolution bits
0
’. For example, a resolution of 6 bits results in ADCDATAx[5:0] being set to ‘0
’ and ADCDATAx[11:6] holding the result.Value | Description |
---|---|
11 | 12 bits (default) |
10 | 10 bits |
01 | 8 bits |
00 | 6 bits |
Bits 20:16 – STRGSRC[4:0] ScanTrigger Source Select bits
Value | Description |
---|---|
10001 - 11111 | Reserved |
10000 | EVSYS_47 |
01111 | EVSYS_46 |
01110 | EVSYS_45 |
01101 | EVSYS_44 |
01100 | EVSYS_43 |
01011 | EVSYS_42 |
01010 | EVSYS_41 |
01001 | EVSYS_40 |
01000 | EVSYS_39 |
00111 | EVSYS_38 |
00110 | EVSYS_37 |
00101 | EVSYS_36 |
00100 | INT0 External interrupt |
00011 | Reserved |
00010 | Global level software trigger (GLSWTRG) |
00001 | Global software edge trigger (GSWTRG) |
00000 | No Trigger |
Bit 15 – ON ADC Module Enable bit
Value | Description |
---|---|
0 | ADC module is disabled |
1 | ADC module is enabled |
Bit 14 – FRZ Freeze in Debug Mode
Value | Description |
---|---|
0 | Do not freeze in Debug mode |
1 | Freeze in Debug mode |
Bit 13 – SIDL Stop in Idle Mode bit
Value | Description |
---|---|
0 | Continue module operation in Idle mode |
1 | Discontinue module operation when device enters Idle mode |
Bit 10 – FSYDMA Fast Synchronous DMA System Clock bit
Value | Description |
---|---|
0 | Fast synchronous DMA system clock is disabled |
1 | Fast synchronous DMA system clock is enabled |
Bit 9 – FSYUPB Fast Synchronous UPB Clock bit
Value | Description |
---|---|
0 | Fast synchronous UPB clock is disabled |
1 | Fast synchronous UPB clock is enabled |
Bit 8 – SCANEN SCAN Enable bit
Bits 6:4 – IRQVS[2:0] Interrupt Vector Shift bits
To determine the interrupt vector address, this bit specifies the amount of left-shift done to the ARDYx status bits in the ADCDSTAT1 and ADCDSTAT2 registers prior to adding with the ADCBASE register.
Interrupt Vector Address = Read Value of ADCBASE, and Read Value of ADCBASE = Value written to ADCBASE + x << IRQVS[2:0], where ‘x’ is the smallest active input ID from the ADCDSTAT1 or ADCDSTAT2 registers (which has highest priority).
Value | Description |
---|---|
111 | Shift x left 7 bit position |
110 | Shift x left 6 bit position |
101 | Shift x left 5 bit position |
100 | Shift x left 4 bit position |
011 | Shift x left 3 bit position |
010 | Shift x left 2 bit position |
001 | Shift x left 1 bit position |
000 | Shift x left 0 bit position |
Bit 3 – STRGLVL ScanTrigger High Level/Positive Edge Sensitivity bit
Value | Description |
---|---|
0 | Scan trigger is positive edge sensitive. Once STRIG mode is selected (TRGSRCx[4:0] in the ADCTRGx register), only a single scan trigger is generated, which completes the scan of all selected analog inputs. |
1 | Scan trigger is high level sensitive. Once STRIG mode is selected (TRGSRCx[4:0] in the ADCTRGx register), the scan trigger continues for all selected analog inputs, until the STRIG option is removed. |
Bits 2:0 – DMABL[2:0] DMA to System RAM Buffer Length Size
Defines the number of locations in system memory allocated per analog input for DMA interface use. As each output data is 16-bit wide, one location consists of 2 bytes. Therefore, the actual size reserved in the system RAM follows the formula: RAM Buffer Length in bytes = 2(DMABL+1).