38.11.20 ADCDMASTAT – ADC DMA Status Register

This register contains the DMA status bits.

Name:	ADCDMASTAT
Offset:	0x1710
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
	DMAEN							RBF0IEN
Access	R/W							R/W
Reset	0							0


Bit	23	22	21	20	19	18	17	16
	WROVRERR							RBF0
Access	R/HS/HC							R/HS/HC
Reset	0							0


Bit	15	14	13	12	11	10	9	8
	DMACNTEN							RAF0IEN
Access	R/W							R/W
Reset	0							0


Bit	7	6	5	4	3	2	1	0
								RAF0
Access								R/HS/HC
Reset								0

Bit 31 – DMAEN DMA Interface Enable bit

When DMAEN = 0, no data is being saved into the DMA FIFO, no SRAM writes occur, and the DMA interface logic is being kept in Reset state.

Value	Description
1	DMA interface is enabled
0	DMA interface is disabled

Bit 24 – RBF0IEN RAM Buffer B Full Interrupt Enable for channel 0

Value	Description
1	Interrupts are enabled and generated when the RBFx Status bit is set
0	Interrupts are disabled

Bit 23 – WROVRERR Write Overflow Error in the DMA FIFO

Set by hardware, cleared by hardware after a software read of the ADDMAST register.

Note: The write always occurs and the old data is replaced with new data because the software missed reading the old data on time.

Bit 16 – RBF0 RAM Buffer B FULL status bit for channel 0

This bit is self-clearing upon being read by software.

Bit 15 – DMACNTEN DMA Buffer Sample Count Enable bit

The DMA interface saves the current sample count for each buffer in the table starting at the ADCCNTB address after each sample write into the corresponding buffer in the SRAM.

Bit 8 – RAF0IEN RAM Buffer A FULL Interrupt Enable for channel 0

Value	Description
1	Interrupts are enabled and generated when the RAFx Status bit is set
0	Interrupts are disabled

Bit 0 – RAF0 RAM Buffer A FULL status bit for channel 0

This bit is self-clearing upon being read by software.