38.11.22 ADCDMAB – ADC DMA Base Address Register

This register contains the base address of RAM for the DMA engine.

Name:	ADCDMAB
Offset:	0x1730
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
	ADDMAB[31:24]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ADDMAB[23:16]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADDMAB[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDMAB[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – ADDMAB[31:0] Base Address for the DMA Interface

BASE ADDRESS for the DMA interface at which to save first class channel data into the System RAM. If first class channel x, x == 0...6, is ready with new available sample data and the DMA interface is currently saving data for channel x to RAM Buffer z (where z ==0 means Buffer A and z == 1 means Buffer B, z depending on x) and the current DMA x-counter value is y (y depending on x), then the DMA interface stores the 2-byte output data value at System RAM address (ADDMAB + (2*x + z)*2(DMABL+1) +2*y. Also, if ADDMAST.DMA_CNT_EN is set to 1, the DMA interface stores (without delay) the value y itself at the System RAM address (ADCCNTB + 2*x + z).