38.11.13 ADCFLTR1 – ADC Digital Filter 1 Register
These registers provide control and status bits for the oversampling filter accumulator, and also includes the 16-bit filter output data.
| Name: | ADCFLTR1 |
| Offset: | 0x15A0 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| AFEN | DATA16EN | DFMODE | OVRSAM[2:0] | AFGIEN | AFRDY | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHNLID[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTRDATA[15:8] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTRDATA[7:0] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – AFEN Digital Filter ‘x’ Enable bit
| Value | Description |
|---|---|
| 1 | Digital filter is enabled |
| 0 | Digital filter is disabled and the AFRDY status bit is cleared |
Bit 30 – DATA16EN Filter Significant Data Length bit
1 (Averaging Mode) and FRACT (ADCCON1[23]) = 1 (Fractional Output Mode).| Value | Description |
|---|---|
| 1 | All 16 bits of the filter output data are significant |
| 0 | Only the first 12 bits are significant, followed by four zeros |
Bit 29 – DFMODE ADC Filter Mode bit
| Value | Description |
|---|---|
| 1 | Filter ‘x’ works in Averaging mode |
| 0 | Filter ‘x’ works in Oversampling Filter mode (default) |
Bits 28:26 – OVRSAM[2:0] Oversampling Filter Ratio bits
| Value | Description |
|---|---|
If DFMODE is ‘ | |
| 111 | 128 samples (shift sum 3 bits to right, output data is in 15.1 format) |
| 110 | 32 samples (shift sum 2 bits to right, output data is in 14.1 format) |
| 101 | 8 samples (shift sum 1 bit to right, output data is in 13.1 format) |
| 100 | 2 samples (shift sum 0 bits to right, output data is in 12.1 format) |
| 011 | 256 samples (shift sum 4 bits to right, output data is 16 bits) |
| 010 | 64 samples (shift sum 3 bits to right, output data is 15 bits) |
| 001 | 16 samples (shift sum 2 bits to right, output data is 14 bits) |
| 000 | 4 samples (shift sum 1 bit to right, output data is 13 bits) |
If DFMODE is ‘1’ | |
| 111 | 256 samples (256 samples to be averaged) |
| 110 | 128 samples (128 samples to be averaged) |
| 101 | 64 samples (64 samples to be averaged) |
| 100 | 32 samples (32 samples to be averaged) |
| 011 | 16 samples (16 samples to be averaged) |
| 010 | 8 samples (8 samples to be averaged) |
| 001 | 4 samples (4 samples to be averaged) |
| 000 | 2 samples (2 samples to be averaged) |
Bit 25 – AFGIEN Digital Filter ‘x’ Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Digital filter interrupt is enabled and is generated by the AFRDY status bit |
| 0 | Digital filter is disabled |
Bit 24 – AFRDY Digital Filter ‘x’ Data Ready Status bit
0’).| Value | Description |
|---|---|
| 1 | Data is ready in the FLTRDATA[15:0] bits |
| 0 | Data is not ready |
Bits 20:16 – CHNLID[4:0] Digital Filter Analog Input Selection bits
These bits specify the analog input to be used as the oversampling filter data source.
| Value | Description |
|---|---|
| 11111 | Reserved |
| ... | |
| ... | |
| ... | |
| 01100 | Reserved |
| 01011 | AN11 |
| ... | |
| ... | |
| ... | |
| 00010 | AN2 |
| 00001 | AN1 |
| 00000 | AN0 |
Bits 15:0 – FLTRDATA[15:0] Digital Filter ‘x’ Data Output Value bits
The filter output data is as per the fractional format set in the FRACT bit (ADCCON1[23]). The FRACT bit must not be changed while the filter is enabled. Changing the state of the FRACT bit after the operation of the filter ended must not update the value of the FLTRDATA[15:0] bits to reflect the new format.