38.11.21 ADCCNTB – ADC Channel Sample Count Base Address Register
This register contains the base address of the sample count in RAM. In addition to storing the converted data of the ADC module in RAM, DMA also stores the converted sample count.
| Name: | ADCCNTB |
| Offset: | 0x1720 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ADCCNTB[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADCCNTB[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADCCNTB[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADCCNTB[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – ADCCNTB[31:0] ADC Channel Count Base Address
SRAM address for the DMA interface at which to save the first class channel buffer A sample count values into the System RAM. If first class channel x, x=0...6, is ready with a new available sample data and the DMA interface is currently saving data for channel x to RAM Buffer z (where z==0means BufferA and z==1means Buffer B, z depending on x), then the DMA interface will increment (+1) the 1 byte count value stored at the System RAM address (ADCCNTB + 2*x + z).
ADCCNTB works in conjunction with ADDMAB. The DMA interface uses ADCCNTB to save the buffer sample counts only if ADDMAST.DMA_CNT_EN is set to 1.