3.8.5 IO3SETTING
| Name: | IO3SETTING |
| Offset: | 0x05 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IDLST3 | CLKDIV[1:0] | OD3SEL | PU3SEL | IO3DIR | IO3DES[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | |
Bit 7 – IDLST3 IO3 Pin Idle or Default Output State Selection
| Value | Description |
|---|---|
| 0 | Idle
state default output value is logic
‘0’ |
| 1 | Idle
state or default output value is logic
‘1’ |
Bits 6:5 – CLKDIV[1:0] Clock Reference Out Frequency Selection
| Value | Description |
|---|---|
| 00 | The clock-out frequency is 6 MHz |
| 01 | The clock-out frequency is 4 MHz (factory default) |
| 10 | The clock-out frequency is 2 MHz |
| 11 | The clock-out frequency is 1 MHz |
Bit 4 – OD3SEL IO3 Pin Open-Drain Selection
| Value | Description |
|---|---|
| 0 | The output pin is not an open-drain pin |
| 1 | The output pin is an open-drain pin |
Bit 3 – PU3SEL IO3 Pin Pull-Up Enable
| Value | Description |
|---|---|
| 0 | The internal pull-up is disabled |
| 1 | The internal pull-up is enabled |
Bit 2 – IO3DIR IO3 Direction
| Value | Description |
|---|---|
| 0 | GPIO output (factory default) |
| 1 | GPIO input |
Bits 1:0 – IO3DES[1:0] IO3 Designation
| Value | Description |
|---|---|
| 00 | GPIO3 pin (GPIO3) |
| 01 | UART transmit activity (TXA) |
| 10 | I2C clock-line low timeout (I2CTO) |
| 11 | Clock reference out (CLKO) (factory default) |
