Output enable rate is the average percentage of time during which tristate outputs are enabled. When non-tristate output buffers are used, the enable rate should be 100%.
Table 2-17. Toggle Rate Guidelines Recommended for Power Calculation| Component | Definition | Guideline |
|---|
| ⍺1 | Toggle rate of VersaTile outputs | 10% |
| ⍺2 | I/O buffer toggle rate | 10% |
Table 2-18. Enable Rate Guidelines Recommended for Power Calculation| Component | Definition | Guideline |
|---|
| β1 | I/O output buffer enable rate | Toggle rate of the logic driving the output buffer |
| β2 | FPGA fabric SRAM enable rate for read operations | 12.5% |
| β3 | FPGA fabric SRAM enable rate for write operations | 12.5% |
| β4 | eNVM enable rate for read operations | < 5% |
