2.3.5.4 LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in the following figure. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different.

Figure 2-23. LVPECL Circuit Diagram and Board-Level Implementation
Table 2-67. Minimum and Maximum DC Input and Output Levels
DC Parameter Description Min. Max. Min. Max. Min. Max. Units
VCCFPGAIOBx Supply Voltage 3.0 3.3 3.6 V
VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V
VOH Output High Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V
VIL, VIH Input Low, Input High Voltages 0 3.6 0 3.6 0 3.6 V
VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V
VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V
VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V
VIDIFF Input Differential Voltage 300 — 300 — 300 — mV
Table 2-68. AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V) Measuring Point1 (V) VREF (typ.) (V)
1.64 1.94 Cross point —
Note:
  1. Measuring point = Vtrip. See Table 2-22 for a complete table of trip points.