2.3.5.2 LVDS

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Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in the following figure. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different.

Along with LVDS I/O, SmartFusion cSoCs also support bus LVDS structure and multipoint LVDS (M-LVDS) configuration (up to 40 nodes).

Figure 2-21. LVDS Circuit Diagram and Board-Level Implementation

Table 2-64. LVDS Minimum and Maximum DC Input and Output Levels
DC Parameter	Description	Min.	Typ.	Max.	Units
VCCFPGAIOBx	Supply voltage	2.375	2.5	2.625	V
VOL	Output low voltage	0.9	1.075	1.25	V
VOH	Output high voltage	1.25	1.425	1.6	V
I_OL¹	Output lower current	0.65	0.91	1.16	mA
I_OH¹	Output high current	0.65	0.91	1.16	mA
VI	Input voltage	0	—	2.925	V
I_IH²	Input high leakage current	—	—	15	µA
I_IL²	Input low leakage current	—	—	15	µA
V_ODIFF	Differential output voltage	250	350	450	mV
V_OCM	Output common mode voltage	1.125	1.25	1.375	V
V_ICM	Input common mode voltage	0.05	1.25	2.35	V
V_IDIFF	Input differential voltage	100	350		mV

Note:

IOL / IOH defined by VODIFF / (resistor network).
Currents are measured at 125 °C junction temperature.

Table 2-65. AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)	Input High (V)	Measuring Point¹ (V)	VREF (typ.) (V)
1.075	1.325	Cross point	—

Note:

Measuring point = Vtrip. See Table 2-22 for a complete table of trip points.