24.4.5.4 Target Interrupt Request Generation

The Target can generate the Target Interrupt Request (SIR), which is an In-Band Interrupt (IBI), to get the attention of the Active Controller. The application of the Target can decide to send a Target Interrupt Request by asserting the SIR bit in the Target Interrupt Request Register along with the source of payload data.

The Target can send up to four bytes of payload data along with the mandatory byte (MDB).

The source of the four bytes of payload data is from the I3CxCLTSIRDAT register. Set the I3CxCLTINT [SIRCTRL] bits to 2'b00 to indicate the source of the payload data from the I3CxCLTSIRDAT register. The I3CxCLTINT [MDB] is meant for the Mandatory Data Byte that is required to be sent after the Target address is transmitted on the line. The application should program the appropriate MDB values depending on the event for which it wants to trigger the SIR.

The status of the IBI generation is updated in the I3CxCLTIBIRESP[IBISTAT], which is informed to the application by the I3CxINTSTA[IBIUPDSTA] interrupt. Upon successful completion of the I3CxCLTIBIRESP[IBISTAT] update, the I3CxCLTINT[SIR] bit is automatically cleared.

The Target does not attempt to issue the IBI and generates the 'Not Attempted (2'b11)' status under the following conditions:

• Active Controller has not assigned the Dynamic Address.
• Active Controller has cleared the assigned Dynamic Address through RSTDAA.
• Active Controller has disabled the SIRINTEN through DISEC CCC (SIRINTEN in I3CxCLTESTA register).
• The Target has switched the role to Controller (applicable only for Secondary Controller configuration).

The I3CxCLTIBIRESP [SIRRESPDATLEN] indicates the number of bytes of data successfully transmitted on the I³C line. A non-zero value indicates the residual data in the case of I³C Controller early termination of payload data. The Target goes to a halt state once the I³C Controller early terminates the SIR payload data and expects the application to flush the Transmit FIFO, and then resumes the Controller by writing into the RESUME bit of the I3CxCNTRL register.