24.4.5.5 Controller Request Generation

The Target can generate the Controller Request (MR) in non-Active Controller mode to request I3C bus ownership from the Active Controller.

The application can decide to send a Controller Request by asserting the MR bit in the I3CxCLTINT.

The status of the IBI generation is updated in the I3CxCLTIBIRESP[IBISTAT], which is communicated to the application by the I3CxINTSTA[IBIUPDSTA] interrupt. Upon successful completion of the I3CxCLTIBIRESP[IBISTAT] update, the I3CxCLTINT[MR] bit is automatically cleared.

The Target does not attempt to issue the IBI and generates the 'Not Attempted (2'b11)' status under the following conditions.

  • The Controller has not assigned the Dynamic Address.
  • Controller has cleared the assigned Dynamic Address through RSTDAA.
  • Controller has disabled the MRINTEN through DISEC CCC (MRINTEN in I3CxCLTESTA register).
  • The Target has already switched the role to Controller.
Figure 24-43. Target to Controller