3.4.6.1 NVM or RAM Based IVT and/or Exception Handler

The PBU uses signals to indicate whether the vector fetched from the Interrupt Vector Table (IVT) during CPU exception processing is from NVM or RAM.

If the IVT is determined to be RAM-based, the PBU must then determine if the exception handler is RAM or NVM-based and act accordingly. If the IVT is determined to be NVM-based, the PBU will either start prefetching the exception handler instruction stream (NVM-based exception handler) or stall (RAM-based exception handler) and prefetch from the most recently active NVM instruction stream.

In all exception return scenarios, usually the first NVM instruction after the return will have already been prefetched and be available within an ISB. If not, the PBU will stall the CPU while it fetches the return target instruction, after which the CPU will continue execution as normal.