3.4.6.2 IVT in NVM
During exception processing, the BMX asserts CPU memory fetch and CPU memory clear. The PBU will recognize this combination as indicative of an IVT vector fetch from NVM and will fetch the vector data in 4 to 7 cycles.
- Exception Handler in NVM:
If the corresponding exception handler is in NVM, the CPU will issue an NVM PFC during exception processing to commence execution from the exception handler. The PBU will see this PFC event and begin prefetching the exception handler instruction stream.
- Exception Handler in RAM:
If the corresponding exception handler is in RAM, the CPU will issue a RAM PFC during exception processing to commence execution from the exception handler. Because the PFC is to RAM, the BMX will stall the PBU after the IVT fetch completes. While stalled, the PBU will recommence prefetching from the most recently active NVM instruction stream.