3.4.6.3 IVT in RAM

During exception processing, the BMX asserts CPU memory fetch and CPU memory clear. The PBU will recognize this combination as indicative of an IVT vector fetch from RAM. The PBU will then enter pause mode, disabling all NVM prefetching for 4 clock cycles or until a PFC occurs.

  • Exception Handler in NVM:

    If the corresponding exception handler is in NVM, the CPU will issue an NVM PFC during exception processing and commence execution from the exception handler. The PBU will see this PFC event, exit pause mode, and then commence prefetching the exception handler instruction stream.

  • Exception Handler in RAM:

    If the corresponding exception handler is in RAM, the CPU will issue a RAM PFC during exception processing to commence execution from the exception handler. The PBU will not see this PFC event, so it will exit pause mode only after the 4-cycle delay. It will then recommence prefetching from the most recent active NVM instruction stream.