24.2.1 Register Bank

The register bank contains all the registers used to program the Controller for different bus modes, timing parameters and enabling or disabling of interrupts.

The register interface is also used for the transmission of commands and Tx data to the Controller and the reception of Rx data, IBI-data, and responses from the Controller/Target transaction module.

There are registers that are mapped to either FIFOs or Queues present in the SRAM.