9.4.1 Architectural Overview
The power monitor system is intended to check the integrity of the internal low-voltage power domains and the system bandgap, as critical system resources depend on them operating within specification. Critical system resources include the CPU, oscillator and PLLs, ADC, comparators and PWM. The power monitor is powered by VDD directly and is not dependent on the low-voltage domains that it is checking. The power monitor also has its own independent clock source and can continue to operate in the event of a clock failure or reconfiguration. A dedicated bandgap is provided to check the system’s bandgap voltage and provide the OV and UV trip points. A state machine provides autonomous operation independent of the system CPU and controls scanning of voltage domains, trip points, indication and Fault injection support. If an OV/UV event is detected, the state machine issues a system Reset and logs the source of the error to be retrieved after the Reset has occurred.
The power monitor is based around a window comparator that utilizes predefined trip points. The OV/UV trip points are programmed during manufacturing and stored in configuration memory that is not accessible or modifiable by user software. The trip point voltages utilized by the comparators are generated by the power monitor’s bandgap and buffered with a reference amplifier. A voltage scaling circuit is provided to scale the internal voltage domains to that of the power monitor’s reference and trip point voltages.
Fault injection mechanisms are provided to verify the power monitor’s input muxing and trip points. A status register provides an indication of Fault injection status.