18.4.1 Excitation Signal Generation

Resolvers are typically designed to operate within a specific excitation signal frequency, commonly 5 kHz or 10 kHz, to ensure accurate and reliable position sensing. The RDC module incorporates a dedicated signal generation unit to drive the resolver with a square wave excitation signal and to provide synchronized ADC trigger pulses for capturing the resolver's output. When the ON (RDCCON[15]) bit is set, the RDC module will assert a clock request for the RDC input clock. To ensure proper operation of the resolver, the input clock source should be configured to produce an input clock with a frequency equal to the desired resolver excitation frequency, multiplied by the selected EXCFDIV (RDCEXCCON[3:0]) and the constant scaling factor of four.

The excitation signal generation unit will divide the RDC clock input by a constant scaling factor of four, and further divide it by the oversampling factor defined by the EXCFDIV divider, in order to produce the excitation output signal and its complement, RDCEXC and RDCEXCI. These output signals, along with external amplifiers and buffers, generate the resolver excitation signal. The excitation signal frequency is given by the following equation:

$F_{EXC}=\frac{F_{RDCCLK}}{4\times (EXCFDIV+1)\times 2}$

Where F_EXC is the excitation output signal frequency, F_RDCCLK is the RDC input signal frequency, and EXCFDIV is the oversampling factor defined in the RDCEXCCON register. This will generate ADC sampling triggers (EXCFDIV+1) times during each half of the excitation square wave.

Figure 18-8 shows the RDC timing diagram.

When the EXCSYNCEN(RDCEXCCON[15]) bit is set, the RDC will count the number of RDC input clock pulses defined by the SYNCCNT(RDCEXCCON[23:16]) (SYNCCNT - 1 pulses). When the specified counter value elapses, the RDC will start the excitation clock output period and ADC sampling trigger and assert the RDC sync pulse signal. The RDC sync pulse signal will be provided to the CIC filter input and will cause it to reload its decimation count (DECIMCNT(CICSTAT[11:0])) value from the filter length (DECIM(CICDECIM[11:0])). The remaining number of cycles until the counter elapses will be readable from the SYNCCNTSTAT(RDCSTAT[15:8]) bitfield. When configured correctly, this delay should allow the CIC filter to provide its output contemporaneously to a controlling software process.

The excitation signal and inverted excitation signal outputs, RDCEXC and RDCEXCI respectively, will be zero when the excitation signal is gated off. The PPS configured to output this signal will be tri-stated by default. The user may force both signals to zero and enable the output when EXCSYNCEN is clear and before the synchronization delay has elapsed by setting the EXCOE bit.