3.6.8.7.4 CPU Write Stalls

Whenever the CPU encounters a write stall, the entire integer pipeline is stalled (because the CPU only supports in-order execution). No subsequent instruction is permitted to move into the W-stage to retire until the write stall is resolved. Different Pipeline stages are explained in FPU Pipeline Operation.

Figure 3-32. CPU Pipeline Coprocessor Interface Flow

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back

Figure 3-33. CPU Pipeline Coprocessor Issue Flow

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back

Figure 3-34. Pipeline and Functional Block Busy Internal/External Structural Hazards

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back

Figure 3-35. FDIV Pipeline and Functional Block Busy Internal/External Structural Hazards

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back

Figure 3-36. External RAW Hazard (CPU Write Data to FPU Read Forwarding)

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back

Figure 3-37. External Raw Hazard (CPU F-REG Write Data to CPU F-REG Read Forwarding)

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back

Figure 3-38. External Raw Hazard (CPU W-REG Write Data to CPU W-REG Read Forwarding)

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back

Figure 3-39. Internal Raw Hazard (FPU Write Data to FPU Read Forwarding)

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back

Figure 3-40. Internal Raw Hazard, External and Internal Structural Hazards

Legend: F = Fetch, A = Address decode, R = Read, X = Execute, W = Write back