Legend: R =
Readable bit; HC = Hardware Clearable bit; HS = Hardware Settable
bit
Bit
31
30
29
28
27
26
25
24
ECCEDATA1[63:56]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ECCEDATA1[55:48]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
ECCEDATA1[47:40]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ECCEDATA1[39:32]
Access
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
R/HS/HC
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – ECCEDATA1[63:32] NVM Read Error Data bits
These bits register the
NVM read data (taking Fault injections into account) when the SEC or DED bit is set in
the NVMECCSTAT register.
DS70005629C
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
