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6.2.12 NVM ECC Error Address Register Name: NVMECCEADDR Offset: 0x302C
Legend: R =
Readable bit; HC = Hardware Clearable bit; HS = Hardware Settable
bit
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 ADDR[23:16]
Access R/HS/HC R/HS/HC R/HS/HC R/HS/HC R/HS/HC R/HS/HC R/HS/HC R/HS/HC Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 ADDR[15:8]
Access R/HS/HC R/HS/HC R/HS/HC R/HS/HC R/HS/HC R/HS/HC R/HS/HC R/HS/HC Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 ADDR[7:4]
ADDR[3:0] Access R/HS/HC R/HS/HC R/HS/HC R/HS/HC R R R R Reset 0 0 0 0 0 0 0 0
Bits 23:4 – ADDR[23:4] ECC Address of Read
Data bits
These bits register the
location of the NVM read data when the SEC or DED bit is set in the NVMECCSTAT
register.
Bits 3:0 – ADDR[3:0] ECC Address (least
significant bits, fixed value 0x0) bits
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