18.3.9.2 Condition Clearing
The CFD condition is cleared:
- After a Reset
- If the monitored source starts toggling again
- If the CFDn flag in the Main Clock Interrupt Flags (CLKCTRL.MCLKINTFLAGS) register is cleared
If it is the main clock that is being monitored and XOSCHF/EXTCLK is the main clock source, changing back to the default start-up clock (OSCHF) will make the main clock start toggling again, clearing the condition.
As long as the failure condition is met, the interrupt will trigger every ten OSC32K cycles.
If these repeated interrupts are not wanted, write a ‘0’ to the Clock Failure
Detection (CFDn) interrupt enable bit in the Main Clock Interrupt Control
(CLKCTRL.MCLKINTCTRL) register.