18.3.9.1 CFD Operation
The CFD feature detects a failed oscillator or clock source by checking for edges on the selected oscillator/clock during a CFD period. A CFD period is 10 cycles on a reference clock, selected by Clock Failure Detection Reference (CFDREF) in the CLKCTRL.MCLKCFDnCTRLA register. In the first 8 cycles of the CFD period, edge detectors will detect edges on the monitored oscillator/clock. The 2 remaining cycles are used to check and issue a CFD condition if no edges are present, and to reset the edge detectors at the end of the CFD period.
When the CFD feature is enabled, it will monitor the selected source from the Clock Failure Detection Source (CFDSRC) bit field in the CLKCTRL.MCLKCFDnCTRLA register. To avoid a CFD event, disable CFD before disabling a monitored clock, or before going to sleep, if the monitored clock stops in sleep.
If the main clock fails, everything running on it will stop. Therefore, a CFD on main clock (CFDSRC == 0 in CLKCTRL.MCLKCFDnCTRLA) is treated differently from a CFD on any other clock:
| CFD Source | ||
|---|---|---|
| Not Main Clock | Main Clock | |
| MAINCLK Source: Not XOSCHF/EXTCLK | MAINCLK Source: XOSCHF/EXTCLK | |
The CFDn interrupt flag in the CLKCTRL.MCLKINTFLAGS register is set, and if the interrupt is enabled, an interrupt request is issued. The Error Controller is informed. | The clock controller will request a Machine Check Reset. | The CFDn interrupt flag in the CLKCTRL.MCLKINTFLAGS register is set, and if the interrupt is enabled, an interrupt request is issued. The Error Controller is informed. The clock controller will switch to OSCHF as main clock. MCLKCTRL.CTRLB will be written to the reset value. The start-up clock source is changed back to its reset frequency. If set, the CLKOUT and CLKOUTDIV bits in CLKCTRL.MCLKCTRLA is cleared automatically |