17.6.1 Control A
Note: There must be at least one cycle (NOP or other instruction) between writing to this register and accessing the RAM to allow the injection logic to be ready.
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PARITY | COMP | ECC2 | ECC1 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – PARITY Inject Parity Error
Writing this bit to ‘1’ will inject a data bus parity error on
the data returned by the next read from RAM. This bit is automatically cleared
after the error has been injected.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Do not inject error |
| 0x1 | ENABLE | Inject error |
Bit 2 – COMP Inject ECC Comparator Mismatch Error
Writing this bit to ‘1’ will inject an ECC comparator mismatch
error on the next read from RAM. This bit is automatically cleared after the
error has been injected.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Do not inject error |
| 0x1 | ENABLE | Inject error |
Bit 1 – ECC2 Inject 2-bit ECC Error
Writing this bit to ‘1’ will inject a 2-bit ECC error on the
next write to RAM. The error is injected into the LSB and the MSB of the parity
data. This bit is automatically cleared after the error has been injected.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Do not inject error |
| 0x1 | ENABLE | Inject error |
Bit 0 – ECC1 Inject 1-bit ECC Error
Writing this bit to ‘1’ will inject a 1-bit ECC error on the
next write to RAM. The error is injected into the LSB. This bit is automatically
cleared after the error has been injected.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Do not inject error |
| 0x1 | ENABLE | Inject error |