17.6.2 Interrupt Flags
This register is set by hardware when an
error is generated as a response to a hardware error or an error caused by error
injection.| Name: | INTFLAGS |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | Configuration Change
Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | PARITYD | PARITYA | PARITYC | COMP | ECC2 | ECC1 | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 5 – PARITYD Parity Error Detected on Write Data
Set when a data bus parity
error is detected on write data. Write this bit to ’1’ to clear
it.
Bit 4 – PARITYA Parity Error Detected on Address
Set when a data bus parity
error is detected on the read or write address. Write this bit to
’1’ to clear it.
Bit 3 – PARITYC Parity Error
Detected on Control
Set when a data bus parity
error is detected on control signals. Write this bit to ’1’ to
clear it.
Bit 2 – COMP Comparator Mismatch
Error Detected
Set when a mismatch between
the duplicated ECC checkers is detected. Routed to ERRCTRL. Write this bit to
’1’ to clear it.
Bit 1 – ECC2 ECC Multibit Error
Detected
Set when a 2-bit (or
more) non-correctable error is detected. Routed to ERRCTRL. Write this bit to
’1’ to clear it.
Bit 0 – ECC1 ECC 1-bit Error
Detected
Set when a 1-bit
correctable error is detected. Routed to ERRCTRL. Write this bit to
’1’ to clear it.
