19.6.5 Interrupt Flags Register

This bit is set when VMON has detected an Overvoltage condition. The flag is cleared by writing a ‘1’ to the bit position. Writing a ‘0’ to this bit has no effect.

This bit is set when VMON has detected an Undervoltage condition. The flag is cleared by writing a ‘1’ to the bit position. Writing a ‘0’ to this bit has no effect.

This bit is set when VMON has entered diagnostic (fault injection) mode. The flag is cleared by writing a ‘1’ to the bit position. Writing a ‘0’ to this bit has no effect.

This bit is set when VMON has exited diagnostic (fault injection) mode, either due to timeout or because CTRLB.DMODE was written to ‘NO’. The flag is cleared by writing a ‘1’ to the bit position. Writing a ‘0’ to this bit has no effect.

This bit is set when VMON is in an illegal state. The flag is cleared by writing a ‘1’ to the bit position. Writing a ‘0’ to this bit has no effect.

This bit is set when VMON is in a Sleep state. Voltage thresholds match the voltage regulator sleep mode output voltage. This flag is permanently set when OSC32K is selected as the main clock source and UPDI is inactive. Any error controller present in the system must be configured in a way that does not cause an unwanted response, such as entering a safe state. The flag is cleared by writing a ‘1’ to the bit position. Writing a ‘0’ to this bit has no effect.

This bit is set when VMON is disabled. The flag is cleared by writing a ‘1’ to the bit position. Writing a ‘0’ to this bit has no effect.

This bit is set when a SLEEP instruction was attempted executed, but was aborted due to an illegal condition. An error is flagged if attempting to enter sleep with CTRLA.SEN = ‘0’ or CPU.SREG.I = ‘0’. The flag is cleared by writing a ‘1’ to the bit position. Writing a ‘0’ to this bit has no effect.