16.2 High-Resolution Mode (Fine Edge Placement)

Table 16-6. High-Resolution Mode Details
Input Frequency	Resolution
300-800 Mhz	up to 78 ps

The PWM Generators may operate in High-Resolution mode to enhance phase, duty cycle and dead-time resolution. A PLL internal to the PWM module locks to the PWM input clock and slices it into 16 pieces to provide high-resolution performance. High-Resolution mode cannot be used with frequency scaling or the clock divider. To enable High-Resolution mode for a given PWM Generator, set the HREN control bit (PGxCON[7]). The HRRDY status bit (PCLKCON[15]) indicates when the high-resolution circuitry is ready, and the HRERR bit (PCLKCON[14]) indicates a clocking error has occurred. When operating in high resolution, Dual PWM mode cannot be used in conjunction with Complementary Output mode.

In the event of a clocking error (HRERR = 1), the HRERR bit must be set to ‘0’ in the software. When ‘0’ is written to HRERR after a clocking error, the High-Resolution mode is disabled and then re-enabled. This is to re-establish the PLL lock for High-Resolution mode. After High-Resolution mode is disabled, the associated outputs will be driven to ‘0’ until the re-enable has been successfully completed.

Note: When using High-Resolution mode, the CLKSEL[1:0] bits (PGxCON[4:3]) must be set to ‘01’ to select pwm_master_clk directly, and the pwm_master_clk must be configured for the correct frequency. Refer to the PWMx Module Timing Requirements within Electrical Characteristics for this value.