3.4.2 Full Register-transfer Level (RTL) Model

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In this simulation mode, the register-transfer level (RTL) model of the PCIESS is used, and the entire data path through the PCIESS is exercised. It requires a third-party verification IP (VIP) model for PCIe. The user is responsible for the VIP model for the PCIe.

When using VIP models, ensure the following:

Verification IP must be configured properly.
- BFM type: indicates type of BFM (0 – Root port and 1 – End point).
- Number of lanes: indicates number of connected lanes.
- I/O size: specifies the size of internal I/O space. The values range from 12 to 24.
- MEM32_SIZE: specifies the size of internal 32-bit addressing memory space. The values range from 12 to 24.
- MEM64_SIZE: specifies the size of internal 64-bit addressing memory space. The values range from 12 to 24.
- PCLK: PIPE clock frequency depends on the signaling rate and PIPE interface width configuration.
The receiver pin for XCVR must not be in an unused state. The following example code snippet is used in the testbench to prevent the transmitter pin from going into an unused state.
```
rxp[i] <=(tx_1b[i]===1'bX || tx_1b[i]===1'bZ) ? 1'b0 : tx_1b[i];
```
```
 rxn[i] <=(tx_1b[i]===1'bX || tx_1b[i]===1'bZ) ? 1'b0 : ~tx_1b[i];
```
The receiver pin for VIP model must not be in an unused state. The following example code snippet is used in the testbench to prevent the transmitter pin from going into an unused state.
```
rx_1b[i] <=(txp[i]==txn[i] || txp[i]===1'bX) ? 1'bZ : txp[i]; 
```
Where,
- i – Number of BFM lanes 
- txp and txn – Transmitter pins from XCVR 
- rxp and rxn – Receiver pins from XCVR 
- tx_1b – Transmitter pin from VIP model 
- rx_1b – Receiver pin from VIP model