54.14.9 PDEC - Position Decoder Electrical Specifications
| AC CHARACTERISTICS | Standard
Operating Conditions: VDDIO=VDDANA 1.71V to 3.63V (unless otherwise
stated) Operating temperature -40°C ≤ TA ≤ +125°C | ||||||
|---|---|---|---|---|---|---|---|
| Param. No. | Symbol | Characteristics | Min. | Typ | Max. | Units | Conditions |
| TP1 | TtPH | TPCK high time | 2/fQEICLK+1.3 | — | ns | VDDIOx(min) -to- VDDIOx(max) | |
| TP3 | TtPL | TPCK low time | 2/fQEICLK + 0.9 | — | ns | ||
| TP5 | TtPP | TPCK input period | 4/fQEICLK+ 2.2 | — | ns | ||
| TP7 | TCKEXTDLY | Delay from External TxCK Clock Edge to counter Increment | — | 4/fQEICLK+20.5 | ns | ||
| TP11 | TPDH | Position Decoder Input High Time | 4/fQEICLK+30.9 | — | ns | ||
| TP13 | TPDL | Position Decoder Input Low Time | 4/fQEICLK+30.9 | — | ns | ||
| TP15 | TPDIN | Position Decoder Input Period | 8/fQEICLK+61.8 | — | ns | ||
| TP17 | TPDP | Position Decoder Phase Period | 2/fQEICLK+15.5 | ns | |||
| TP21 | TPDFH | Filter Time to Recognize Low, with Digital Filter | 4/fQEICLK+20.5 | — | ns | ||
| TP23 | TPDFL | Filter Time to Recognize High, with Digital Filter | 4/fQEICLK+20.5 | — | ns | ||
| TP24 | fQEICLK | GCLK for PDEC | — | 200 | MHz | ||
Note:
- These values are based on simulation. They are not covered by production test limits or characterization.
