2.7.3.4 Write Leveling

After the third step, the controller enters the write leveling mode. Any DFI compliant controller must follow this Write Leveling sequence to complete the training step:

1. To enter the Write Leveling mode, the controller must issue Mode Register Set (MRS) to MR1 for DDR3/DDR4, MR2 for LPDDR3, and set the write leveling enable bit (DFI_WRLVL_EN = 1).
2. After detecting DFI_WRLVL_EN =1, the Training IP starts the training algorithm and aligns CLK to DQS. Write leveling is a JEDEC defined method used to detect 0 to 1 transition on CLK by DQS.
3. DQS samples the CLK value and feeds it back on the prime DQ on the DRAM DQ byte lane.
4. When the prime DQ value transitions from 0 to 1, CLK is aligned to DQS within the JEDEC specified timing limits. The Training IP performs this procedure on all byte lanes concurrently.
5. The controller sends continuous strobe (DFI_WRLVL_STROBE) pulses to capture DFI_WRLVL_RESP. DFI_WRLVL_STROBE initiates the capture of DFI_WRLVL_RESP within the PHY DQ bus.
6. The Training IP asserts DFI_WRLVL_RESP = 1 indicating the completion of Write Leveling to the controller.
   Note: In the Fast Simulation Mode, PHY ignores the WRLVL request without responding. The controller must bypass the write leveling, read gate leveling, and read eye training (Read Leveling) stages.
7. When the controller receives the DFI_WRLVL_RESP asserted signal, it de-asserts the write to mode register MR1 and also de-asserts DFI_WRLVL_EN to disable write leveling enable bit.
8. The delay values detected for each byte lane are stored in the PHY lane controller. The following figure shows the controller sampling DFI_WRLVL_RESP and disabling DFI_WRLVL_EN.