2.7.3.9 Simple Burst Read

This step describes simple burst read operation. Similar to WRITE, there are two Timing parameters the controller must be aware of: trddata_en and tphy_rdlat. After issuing DFI READ command on control interface, Controller must assert DFI_RDDATA_EN after trddata_en clocks. The PHY responds to the READ command and DFI_RDDATA_EN with DFI_RDDATA and DFI_RDDATA_VALID. The following figure shows the sequence of events for a simple burst READ operation.

Figure 2-39. DFI Read Burst Example
Figure 2-40. RDDATA On DFI - 16-Bit BL8 On DRAM Translate To DFI 128 BITS (4 X 32)
Figure 2-41. RDDATA On DFI - 32-Bit BL8 On DRAM Translate To DFI 256 BITS (4 X 64)

Data on DFI_RDDATA is valid only when DFI_RDDATA_VALID is asserted. After receiving READ command, PHY responds with Read Data and Read Data Valid signals within (trddata_en + tphy_rdlat) cycles. PHY latencies associated with DFI-to-DRAM and DRAM-to-DFI are added to DFI timing, trddata_en and tphy_rdlat. For 16-bit interface, 128-bits of Data (16 x 8 (BL8)) is transferred to Controller on a single DFI clock cycle.

The timing parameters trddata_en and tphy_rdlat together define maximum number of cycles from assertion of READ command to assertion of DFI_RDDATA_VALID signal.

DFI dictates a timing relationship between DFI_RDDATA_EN and DFI_RDDATA_VALID specified by tphy_rdlat. DFI does not dictate exact number of cycles. Typically, DFI_RDDATA_VALID can assert any time prior to max delay. DFI_RDDATA_VALID is trained and DFI_RDDATA is valid only when DFI_RDDATA_VALID is asserted.